Embodiments of the inventive concept relate generally to electronic memory technologies. More particularly, embodiments of the inventive concept relate to bitline precharge voltage generators and semiconductor memory devices comprising bitline precharge voltage generators.
Dynamic random access memory (DRAM) is a form of volatile memory that stores data using capacitors. In a DRAM, each memory cell comprises a storage capacitor that can store charges corresponding to a logical “0” or a logical “1”, and an access transistor that controls access to the storage capacitor. The access transistor typically has a gate connected to a wordline, and a channel connected between a bitline and the storage capacitor.
The storage capacitor tends to leak charges, so the memory cell must be refreshed periodically to retain stored data. The memory cell is typically refreshed by reading data from the storage capacitor and rewriting the data in the storage capacitor. To read the data from the storage capacitor, a bitline precharge circuit precharges the bitline before a voltage is applied to the wordline to turn on the access transistor. Once the access transistor is turned on, a bitline sensing circuit senses a voltage change on the precharged bitline to detect data stored in the storage capacitor. Thereafter, the memory cell is refreshed by applying charges to the storage capacitor based on the detected data.
To accurately detect the data stored in the storage capacitor, the bitline must be precharged with a stable voltage. However, in high speed DRAM devices, it can be difficult to achieve a stable bitline precharge voltage.